The present invention relates to a method of drawing a pattern such as a semiconductor IC pattern on a wafer by means of a charged beam using a main deflector having a large beam deflection width and a subdeflector having a small beam deflection width.
Recently, a method of drawing a semiconductor IC pattern with a charged beam by the double deflection system, combining a main deflector having a large deflection width and a subdeflector having a small deflection width, has been developed as a method of drawing a pattern of a semiconductor IC, such as an LSI, on a mask or on a wafer by means of a charged beam, especially an electron beam, with high precision at a high speed. A main deflection width is set to be, e.g., 500 .mu.m, and a subdeflection width is set to be, e.g., 30 .mu.m. It is difficult to obtain a high-speed D/A converter of a large number of bits required for a wide deflection scanning range with high precision at a high speed. Therefore, in a system called a double deflection system, a D/A converter of a large number of bits is used to drive the main deflector to position a beam at a reference position in a subdeflection area and then a high-speed D/A converter of a small number of bits is used to drive the subdeflector to draw a pattern. In this system, a beam deflection rate is increased throughout a drawing area and the drawing throughput is expected to be improved.
A typical example of a conventional method of drawing by a double deflection system will now be described with reference to FIG. 1. Referring to FIG. 1, LSI chip area 10 having an LSI pattern formed based on a CAD (Computer Aided Design) output is illustrated. Of the drawing, hatched regions 11 to 13 are pattern regions. Of regions 11 to 13, patterns included in regions 11 and 12 are not repeating type, but region 13 includes repeating type patterns such as memory cells.
First, chip area 10 of FIG. 1 is divided into a plurality of (three, in this case) frame regions 10a, 10b, and 10c each of which is covered by main deflection. Accordingly, widths of frame regions 10a to 10c are respectively determined by maximum deflection widths P1, P2, and P3 of a main deflection beam. Patterns in respective frames 10a to 10c are then divided into a plurality of subfield regions 11a, 11b,..., 12a, 12b,..., and 13a, 13b,...13h covered by subdeflection, as shown in FIG. 2. As is apparent from FIG. 2, since region 11 is completely included in frame region 10a, no problem is posed. In region 12, subfield region 12c is divided into two portions which are included in frames 10a and 10b, respectively, and divided portions of subfield region 12f are included in frames 10b and 10c, respectively. Accordingly, a pattern in subfield region 12c may be undesirably separated into frames 10aan 10b.
FIG. 3 shows an example of division of subfield region 10. In FIG. 3, a very fine pattern 15 with a width on the order of microns, which is included in subfield region 12c, is further divided into two patterns 15a and 15b on the order of submicrons, and processed as pattern data for frames 10a and 10b, respectively. It is very difficult to draw such a very fine pattern on the order of submicrons. Further, patterns 15a and 15b must be drawn independently to form single pattern 15, resulting in increases in the number of patterns to be drawn, the pattern drawing time, and the number of pattern data.
In pattern region 13, as shown in FIG. 4, an identical pattern is repeated in four subfields 13e to 13h. However, pattern 13e-1 in subfield 13e is to be processed as two patterns by frame division. Although four identical patterns are present in the pattern region 13, three identical patterns in subfields 13f to 13h and another pattern in subfield 13e should be processed in frame 10c.
As described above, with the prior art method, when identical patterns are repeatedly drawn with a beam by a double deflection system, regularity of pattern repetition is lost near the frame boundaries. Therefore, pseudo micropatterns on the order of submicrons are formed to make it impossible or difficult to perform precise drawing processing. In addition, the number of drawing figures, the drawing time, and the number of pattern data are increased due to defective frame division of the pattern.
Rapid advances in ICs are expected to lead to micropatterning and an increase in the number of chip patterns in ICs and in time required for processing. Therefore, the above problems typically occur to make it difficult to improve the drawing throughput of a drawing apparatus with an electron beam.